1. Field of the Invention
The present invention relates to a semiconductor memory device and more specifically a row decoder which activates word lines.
2. Description of the Related Art
In recent years, DRAMs (Dynamic Random Access Memories) using one-transistor/one-capacitor memory cells have made much progress in packing density and microstructuring because of improvements in memory cell structure and advances in fine-pattern processing technology and circuit design technology. Meanwhile, logic circuits with no DRAM have made progress in microstructuring and low-voltage version faster than DRAMs because the microstructuring directly leads to higher packing density and increased speed.
In the DRAMs, on the other hand, the voltage written into each memory cell and the voltage applied to the gate electrode of each transistor that connects a memory cell and a bit line cannot be scaled as much as the voltage that controls a logic circuit (logic voltage) because of stringent specifications to leakage current. Thus, in recent years a DRAM has been developed which uses a two- or three-supply-voltage system in which the supply voltage for the logic circuit surrounding DRAM and the supply voltage for a circuit surrounding the memory cells are different.
As this type of related technique a technique to transfer a high voltage to word lines with no voltage drop is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-63795.